- 您现在的位置：买卖IC网 > Sheet目录331 > IPTR-DSPBUILDER (Altera)DSP BUILDER SOFTWARE
3–8
Chapter 3: Design Rules and Procedures
Frequency Design Rules
The RTL view illustrates the effect of this truncation. The parallel adder required has a
smaller bit width and the synthesis tool reduces the size of the multiplier to have a
9-bit output ( Figure 3–7 ).
Figure 3–7. 3-Tap Filter with BusConversion to Control Bit Widths in Quartus II RTL Viewer
f For more information, refer to “Fixed-Point Notation” on page 3–2 .
Frequency Design Rules
This section describes the frequency design rules for single and multiple clock
domains.
Single Clock Domain
If your design does not contain a PLL block or Clock_Derived block, DSP Builder uses
synchronous design rules to convert a Simulink design into hardware. All DSP
Builder registered blocks (such as the Delay block) operate on the positive edge of the
single clock domain, which runs at the system sampling frequency.
The clock pin is not graphically displayed in Simulink unless you use the Clock block.
However, when DSP Builder converts your design to VHDL it automatically connects
the clock pin of the registered blocks (such as the Delay block) to the single clock
domain of the system.
The default clock pin is named clock and there is also a default active-low reset pin
named aclr .
By default, Simulink does not graphically display the clock enable and reset input
pins of the DSP Builder registered blocks. When DSP Builder converts a design to
VHDL, it automatically connects these pins. You can access and drive these optional
ports by checking the appropriate option in the Block Parameters dialog box.
1
DSP Builder Handbook
Simulink issues a warning if you are using an inappropriate solver for your model.
You should set the solver options to fixed-step discrete when you are using a single
clock domain.
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
IR11662SPBF
IC CNTROL SMART RECTIFIER 8-SOIC
IR1166STRPBF
IC MOSFET DRIVER N-CH 200V 8SOIC
IR11672ASPBF
IC MOSFET DRIVER 200V 8-SOIC
IR1167ASTRPBF
IC SMART SECONDARY DRIVER 8-SOIC
IR11682STRPBF
IC MOSFET DRIVER DUAL 200V 8SOIC
IR1168SPBF
IC MOSFET DRIVER DUAL 200V 8SOIC
IR1176STR
IC DRIVER RECT SYNC 5V 4A 20SSOP
IR2010SPBF
IC DRIVER HIGH/LOW SIDE 16SOIC
相关代理商/技术参数
IP-TRIETHERNET
功能描述:开发软件 Triple Spd Ethernet MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-TRIETHERNETF
功能描述:开发软件 3x Spd Ethernet MAC MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPTV-OPTION-INS970
制造商:3M Electronic Products Division 功能描述:IPTV OPTION FOR INS970
IPU039N03L G
功能描述:MOSFET N-CH 30V 50A 3.9mOhms RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube
IPU039N03LG
制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:OptiMOS?3 Power-Transistor Features Fast switching MOSFET for SMPS
IPU039N03LGXK
制造商:Infineon Technologies AG 功能描述:Trans MOSFET N-CH 30V 50A 3-Pin(3+Tab) TO-251
IPU04N03LA
功能描述:MOSFET N-CH 25V 50A IPAK RoHS:否 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件
IPU04N03LA G
功能描述:MOSFET N-CH 25V 50A IPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件